Voltage comparator of stored samples of plural modulated pulses and controlling threshold gate



Jan. 29, 1963 H. BLASBALG 3,076,144

VOLTAGE coMPARAToR oF sToRED SAMPLES oF PLURAL MODULATED f PULsEs AND CONTROLLING THREsHoLD GATE BY WHL..

3,0 76,144 PLURAL MODULATED LD GATE H. L. BLASBALG OF STORED SAMPLES OF D C SHO Jan. 29, 1963 VOLTAGE COMPARATOR PULSES AN ONTROLLING THRE 14 Sheets-Sheet 5 Filed Jan. 14, 1959 amm@ m www M M www m u n znea rvu jjn INVEOR.

Jan- 29, 1963 H. L. BLAsBALG 3,076,144

VOLTAGE COMPARATOR OF STORED SAMPLES OF PLURL MODULATED PULSES AND CONTROLLING THRESHOLD GATE Filed Jan. 14, 1959 14 sheets-sheet 4 H. L. BLASBALG Jan. 29, 1963 3,076,144 VOLTAGE COMPARATOR 0F sToRED SAMPLES oF PLURAL MODULATED PULSES AND CONTROLLING THRESHOLD GATE Filed Jan. 14, 1959 14 Sheets-Sheet 5 md og NOx Jan- 29, 1963 H. L. BLAsBALG 3,076,144

VOLTAGE coMPARAToR oF sToRED SAMPLES oF PLURAL MODULATED PULsEs AND coNTRoLLING THREsHoLD GATE Filed Jan. 14, 1959 14 Sheets-Sheet 6 Ebb INVENTOR. #ff/MN Misa/ u 6 BY W.

Jan. 29, 1963 H. l.. BLASBALG 3,076,144

OMPARATOR OF STORED SAMPLES OF PLURALMODULATED PULSES AND CONTROLLING THRESHOLD GATE VOLTAGE C Filed Jan. 14, 1959 14 Sheets-Sheet 7 MASA LK Jan. 29, 1963 H. L. AsBALG 3,076,144

VOLTAGE coMPA 0R sTo D sA LES PLURAL MODULATED PULs AN oNTRoLLIN HRE LD GATE Filed Jan. 1.4, 1959 14 sheets-sheet e Jan- 29, 1963 H. L. BLASBALG 3,076,144

VOLTAGE coMPARAToR oF sToRED SAMPLES oF PLURAL MODULATED PULsEs AND coNTRoLLING THREsHoLD GATE Filed Jan. 14, 1959 14 Sheets-Sheet 9 -..l 1 lnx ,W A

Jan. 29, 1963 H. L. BLASBALG 3,076,144

VOLTAGE COMPARATOR OF STORED SAMPLES OF PLURAL MODULATED PULSES AND CONTROLLING THRESI-IOLD GATE Filed Jan. 14, 1959 14 Sheets-Sheet 10 w WMM Jan. 29, 1963 H. 1 BLASBALG 3,076,144

OMPARATOR OF STORED SAMPLES OF' PLURL MODULATED SHOLD GATE VOLTAGE C Filed Jan. 14, 1959 PULSES AND CONTROLLING THRE 14 Sheets-Sheet 1l :-m. fr

Jan. 29, 1963 H. L. BLASBALG 3,076,144

VOLTAGE coMPARAToR 0E sToEED SAMPLES oF PLURAL MODULATED PULsEs AND ooNTRoLLNG THEEsHoLD GATE Filed Jan. 14, 1959 14 Sheets-Sheet 12 tino our

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VOLTAGE Filed Jan. 1959 H L. BLASBALG 3,076,144

COMPARATOR OF" STORED SAMPLES OF PLURAL MODULATED PULSES AND CONTROLLING THRESHOLD GATE 14 Sheets-Sheet 15 1 l l I x l 1 Jan. 29, 1963 H. l.. BLAsBALG 3,076,144 VOLTAGE coMPARAToR oF sToRED SAMPLES oF PLURAL MODULATED PULSEIS AND CONTROLLING THRESHOLD GATE Filed Jan. 14, 1959 V 14 Sheets-Sheet 14 me.. n

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United States Patent Ofice 1 dldddd Patented Jan. 29, i953 This invention relates to a statistical analyzer and particularly to an analyzer for determining the presence or absence of modulation on a radiated signal.

The irst step of electronic counter measures consists in determining the kind, position and characteristics of the various radiated energy from the enemy electronic devices. It is, accordingly, customary to send ferret vehicles to linger print the electronic devices providing radiation..

One of the characteristics to be determined is the presence or absence of modulation on the detected radiation wave.

The present invention relates to an electronic system for testing at predetermined sequences the envelopes of the detected radiation wave by taking samples at preselected time positions along the envelope of the wave and alternately supplying the samples to a pair of storage devices. The stored samples are then fed to a pair of potential generating devices to provide electrical quantities proportional to the width of the envelope at sampling positions. A sum and difference device is then utilized to provide the sum and difference of the quantities which are then compared to control a yes or no gate to signal the presence or absence of modulation on the investigated wave.

In a construction according to the invention a first and second generator receive alternate envelope samples and provide the output thereof to a difference amplier and to an adder device after which the stun and the difference are applied to a comparator which controls the operation of a gate tube to control a blocking oscillator and supply yes or no signals to a suitable recorder.

It is, accordingly, an object of the invention to provide an improved modulation detector.

'It is a further object of the invention to provide a small-sized lightweight analyzer for determining the presence or absence of modulation on a detected wave.

Other objects and advantages of the invention will be apparent from the following detailed descriptions taken in conjunction with the accompanying drawing, in which:

FIG. 1 is a block diagram of a statistical analyzer according to the invention;

FIG. 2 is a graphical presentation of the signals through the analyzer;

FIG. 3 is a schematic circuit diagram of the analyzer of FIG. l;

FIG. 4 is a graphical presentation of the characteristics of the difference ampliiier under various load conditions;

FIG. 5 is a simplied circuit diagram of the diiierence amplifier;

FIG. 6 is a block diagram of a modification according to the invention;

FIG. 7 is a graphical illustration of the signals through the modification according to FIG. 6;

FIG. 8 is a schematic circuit diagram of the modiiication according to FIG. 6;

FIG. 9` is a simplified showing of a section of the modification according to FIG. 6;

the

FIG. l1 is a block diagram of a further modification ac cording to the invention;

FIG. l2 is a schematic circuit diagram of the modification according to FIG. 1l;

FIG. 13 is a graphical presentation of the operation of the comparator according to FIG. 11; and

FIG. 14 is a graphical presentation of the comparator cathode impedance operation.

In an exemplary embodiment according to the invention the detected wave as received from any suitable detecting device is periodically sampled by measuring the amplitude of the envelope lil of the detected wave, as shown in FIGURE 2a, at suitable time positions such as a indicated by the numerals l and 2 applied between the indicators 11 between the envelope itl and the zero base lever 12 in FIGURE 2a. rhe samples X1 and X2 are alternately supplied to suitable sample storing devices such as capacitors and the respective samples X1 and X2 FIGURES 2b and 2c are periodically read out to a iirst potential generator 14 and a second potential generator 16 as shown in FIGS. 1 and 3. The generators 14 and 16 control a difference ampliiier 13 which in turn feeds an adder 2t?. The output of the difference amplifier is also supplied through a magnitude control circuit 22 after which the output FIGURE 2d of the magnitude control circuit and ot the adder Ztl FEGURE 2e are applied to a comparator 24 which in turn supplies a control potential FIGURE 2f to a gate tube 2o to which periodic read pulses *titi FIGURE 2g are also supplied. The output FIGURE 2h ot the gate tube provides yes pulses and controls a blocking oscillator 25 when the comparator 24 indicates modulation of the investigated wave.

The potential generators le and 16 are preferably grid controlled tubes having the grids 1S and i7, as shown in FIGURE 3, controlled by the quantities X1 and X2 respectively representing the height of the envelope 1li at 4 the sample times. The grid controlled generators 1d and 16 have equal load resistors Sti and 32. in the cathode to ground circuit so that the output is proportional to the grid supply X1 or X2.

The difference amplifier 18 is constituted by a pair of amplifiers 34 and 36 being respectively controlled from the tubes 14 and 1t. The potential of the plates of the ampliers 34 and 36 are in turn applied to the grids 35 and 37 of tubes 33 and it@ to control the amplitude of the output s1gnal to the grid 4l of tube 42.?. The poten- .tial across the adder pentode tube 2@ is applied to the grid i4 of tube do having a load resistor 47 in the plate c1rcuit. Tubes 42 and do supply current through pentode 4d to provide a potential from the plate 52 of tube 46 across a potentiometer Sli connected between the I plate Si?. of tube 46 and a source 53 of bias potential heremindicated as -300 Volts. An intermediate tap 54 on .the potentiometer 5d picks 0H a control potential which 1s supplied to the grid 56 of gate tube Z6. A read pulse lagging behind the output of the generators 14 p and 16 by a time interval et of 35 seconds so that the PIG. 10 is a simplified showing of the slicer ofFIG. 6;

read out will not be disturbed by any transient in the signal caused by switching operations is applied through` aicontrol transformer 62 the secondary 63 of which is in the biasing line 64 to the grid 65 of gate tube 26 so that the read pulse provides a positive pulse on the transformer secondary 63 to drive the control grid 65 of the gate tube 26 positive so that the application of a positive potential to the grid 56 will cause current tlow through gate tubev Z6 and the transformer 7) which initiates a pulse in secondary 72. to grid 7l. to initiate block-l ing oscillating action in tube 72 and secondary 74 supplies an output signal '76 to any suitable indicating device.

In the operation of this simpliiied form of the invention the storage samplers alternately sequentially sample the envelope of the detected wave and the alternate samples X1 and X2 are held on suitable storage devices such as condensers (not shown) for a time duration equal to twice the sampling period a. The period a between samples may be varied -as desired from 500 nseconds to 125 ,useconds This condition is indicated at FiG. 2a by the amplitude signals 1 and 2 as indicated above.

The input samples X1 and X2 control the generators 14 and 16 which provide potentials proportional to the samples X1 and X2 which proceed through their respective amplifiers 36 and 34 of the difference and sum amplifier device. The diierence and sum outputs are proportional to (X1 X2) and (Xd-X2) respectively, these are then applied to comparator 24 as shown at FIGS. 2d and 2e. FIG. 2a' showing {XXI-X2) output from the difference amplifier and the positive magnitude circuit to the statstica-l comparator 24, where is the voltage gain of the difference amplifier 28 and magnitude circuit 22. FIG. 2e shows '7(X1-l-X2) output from the addition amplier to the statistical comparator where the fy is the voltage gain of the addition circuit. The output of the comparator 24 is equal to (X1 X2) -/(X1+X2) as shown at 28.

The read pulse 60 is applied to grid 65, 35 ,r/.seconds after the initiation of conduction in the tubes 14 and 16 by the samples X1 and X2. Whenever the output of the comparator 24 is in excess of the preset cutol threshold bias level 78, FIGURE 2f, of the grid 56 of the gate tube 26 the read pulse will actuate the gate 26. This in turn triggers the blocking oscillator and provides the yes pulse 76. The yes indication, in the form of a pulse 76, is stored in any suitable indicator or counter. Output or" difference and positive magnitude circuitry -(X1X2) Gain through amplier and dierence system= Input to comparator from difference circuitry .X1-X2) Output of adder-(X1-l-X2) Gain through amplifier and adder system=fy Input to comparator' from addition circuitry='y( K14-X2) Output of comparator: (X1 X) ,/(X1+X2) Stada-mar.) Gain of comparator=A Input to gate tube=rl(( X1 2) (X,+X2)) AGU; -X2 -(X1+X,)) e

there will be a Yes indication at the counter. e is the threshold level that is necessary to obtain hold-off conditions as a safeguard against false noise triggering indications.

Note that the higher the comparator gain A, the lower the threshold error e/A. Physically e/A can never be zero. This is characteristic of all threshold devices.

The simplified circuit of FIGS. 1 3 is very compact and can be mounted in a minimum of space. However this circuit has three undesirable characteristics.

1) In order to limit the number of tubes, the difference amplifier must be operated at its maximum gain.

(2) Extreme linearity is required in the addition and subtraction operation since these occur prior to comparison.

(3) Driftis a serious problem;

Because the difference amplier 18 is operated at maximum gain, the grid 84 to cathode bias is about 0.85 at a reference level of v. at the grids 84. This operating point is necessary for maximum gain, gm. The constant current pentode 20 in the cathode 86 of the difference amplifier allows for a maximum difference of 1.7 volts between the grids at the 100 v. reference level, see FIG. 4. This difference is diminished if the reference is raised above 100 v., and increased if the reference is lowered below 100 v.

The foregoing can be seen from FIGS. 4 and 5 and from the following derivation:

Where each amplilier 34 and 36 is provided with a load resistor 90 of 18K value in series between applied voltage Ebb of 300 v. at terminal 92 and plate 88 and where the drop across pentode 20 of 100.85 v. with grid reference at grid 94 of 100 v. as determined by the setting of control resistor 96 (curve 100); Eb at pentode 20 is 100.85 v. and Ebb is 0.85 v. When the grid reference is reduced to 80 v. (curve `102) Eb is reduced to 81-17 v. and Ebb raised to 1.17 v. Also when the grid reference is raised to v. (curve 104) Eb increases to 120.4 v. and Ebb falls to 0.4 v.

It can be seen that when a 1.7 volt dilference is applied between grids, the voltage yacross the difference amplifier 18 is reduced by 0.85 volt at the cathode end. Hence, the grid to cathode volt-age goes to zero and saturation results. Saturation causes nonlinear operation at the sum and difference outputs. Thus, the mathematical charactera istics of the circuit are no longer valid. Hence, the foregoing discussion implies low level operation.

In order to eliminate the necessity for low level operation, the circuit was `modified as shown in FIGS. 6 and 8 to provide a pair of amplitude comparators 110-112 with the comparators being amplitude differential ampliiers. Each of the amplifiers 110 and 1112 feeds a level Slicer 114 or 116 each of which in .turn feeds a gate 1118 or 120. rSince the amplitude comparators are differential ampliers there is no need for linearity as the output is either positive or negative. A positive output from either comparator 110 or l112 actuates the respective slicer 114 or 116.

As shown in FIG. l0, the Slicers 114 and 116 each consists of a pair of discharge paths 500 and 502. The path 500 having a plate 504, a cathode 506 with control grid 154, while path S02 has a plate 160, a cathode 508 and control grid 510. Cathodes 506 and S08 are grounded through common cathode resistor 512. Plate 160 is supplied from a 300 volt source through plate resistor 514 and plate 504 is supplied from the 300 volt source over resistor 516. Grid S20 is connected to plate 504 by way of capacitor 522 and parallel resistor 524 and in turn is connected across cathode resistor 512 by capacitor 526 with discharge resistor 528 in parallel.

As shown in FIGS. 8 and 9 the cathodes of tubes 14 and 16 are connected over potentiometers 130 and 132 of 100 v. The amplitude comparators 1110 and 112 each consist of a pair of discharge paths 136 and 138 with the cathodes feeding through a pentode 140 to ground. An intermediate point 142 in the potentiometer 132 providing a factor KX1 is directly connected to the grid 144 of the path 136 of the. directly following comparator 110 or 112. The respective cathyodes of tubes 14 and 16 are cross connected to the grids 146 of the alternate path 138. The path 138 has a load resistor 148 in the cathode lead, The plate of path 138 is connected over potentiometer 150 .to a bias of 300 v. with a mid tap 152 connected to control grid 154 of respective slicer 114 or 116. Plate 160 `of the slicer is connected over resistor 162 to grid 164 of the gate. Negative bias is normally applied to grid 164 over resistor 166.

The design of `the simple resistance network, as shown in FIG. 9, is such that there is no possibility of both l-mow ..X1l+mo X220 I The-ratio I' v 1e-m0 K"1+m0 is obtained at the outputs of the amplifiers by means of the two potentiometers 130 and 132. Terminals 17 0-172 of these potentiometers are connected to the respective ampliiiers as shown in FIG. 9 and'ter-minals 142 to refer-k ence voltage E: 100 v.

The center tap of each potentiometer isconnected to the grid of its respective comparator. Terminals 176 and 172 of the potentiometers 130 and 132 are criss-crossed to provide the physical circuitry representing the func-- tions-KX-l-X2 and KXz-Xl. Terminal 172 of channel X1 is connected to grid 174 of channel X2, and terminal 170 of channel X2 is connected to grid -146 of channel X1. K is obtained by moving the center tap 142 up and down where Ir=R See FIG. 9.

The slicers in each channel have a resolution of the order of a fraction of 1 volt, and the outputs of each is 50 v. or more. The input level to the input grids 154 of the slicers is adjusted to 165.3 v. or 1 v. below the triggering level of 166.3 v.

The operating characteristics of these Slicers is tabulated below:

The pentodes 140 in the cathodes of the .comparators are constant current generators. Therefore, as long as the input lgrids 1144 of each lcompara-tor are at the same voltage level, this level can be increased as much as 5t) volts `above the volt referencefand the comparator output level will remain constant within i2 volts about 241 volts. This necessitated an adjustment of the 162 v. level `for each particular value of signal 4modulation M.

The preceding discussion of the system design shows that lthe slicers are actuated with either XXI-X2 or KXZKl. The slicer is -an on-ol device. Since there is a l v. diiferential biasing threshold at the grids of the slicers, they will be actuated when either KX1 2X2+ (Referred to Jthe grids of KX2X1+ the respective comparator.)

Since GZO, either KX1X2+50 mv. or KXZXl-i-SO mv. is necessary condition for triggering.

IHigh precisionpower supplies are necessary in order to maintain critical voltage levels. This is inherent in all statistical analyzers since the results are often critically a function of the threshold setting.

During the operation of the Statistical Analyzer, it was foundthat the B+ and B- voltages had to be very carefully monitored and corrected for drift in order to obtain reproducible results.

The circuit was further modified to reduce drift, secure plate stability of the comparators and improve the operation `as shown in FIGS. 10, 11 and 12.

The weighting potentiometers and 132 have been directly grounded eliminating the +10() v. biasing potential.

The Slicers have been grounded eliminating the biasing.

Plate stability in the amplitude comparators has been improved by inserting an equalizing potentiometer 310 between the cathodes of the comparator and by inserting load resistors 312 and 314 in the plate circuits. Because of the load resistors and since all points on the comparators are referred to ground it was found desirable to insert 100 ohm resistors 32) and 322 in series With the grids 324 and 326 to suppress parasitic amplier oscillations in the comparators. The analyzer channel comparator gains have been increased slightly by the insertion of an additional `amplifier stage 330 in each channel, in order to compensate for the loss or gain by the insertion of the plate load resistors 312 and 314.

Furthermore, the comparator operation of the modified analyzer has now been improved in three ways, see PIG. l2;

(i) The grid reference can be raised +20 v. above ground without changing the plate output voltage by as much as 1 mv.

(ii) The frequency response of the comparator has been `increased to over 30 mc.v due to the 5.1K loading in the plates.

(iii) The tolerable range of dilference of potential between the grids of the comparator has been increased to 4.5 volts. This is due to two changes in the circuitry;

(a) the grid potential zero reference is now at ground, r-(b) the 5.1K loading of the plates (see FIG. 13).

The improved stability of plate potential with variation of grid reference of the comparators is due to the potentiometers 310 in the cathodes and the 5.1K loading of the plates. These potentiometers have four functions:

(a) They compensate for that 5% tolerance of the plate load resistors,

(b) They compensate for the lateral posi-tion difference of the grid bias curves between each section of the double triode,

(c) They tend to equalize the rp slope of each tube section,

(d) They compensate for the slight increase in current through the constant current pentode due to increase in plate voltage.

The grid reference level of the comparators should not ordinarily be raised above ZD v. the reason being that the constant current pentode behaves as a perfect adder. A grid reference increase of 20 v. at the comparator grids is retiected as a corresponding increase at the plate of the pentode. This increase is shown in FIG. 14 where load line A of 110 is shifted to position B, 20 v. to the r-ight of A, and quiescent operating point orto position B. Quiescent operating point B is just over the maximum dissipation of the tube. IOn the other hand, a grid reference level increase of 50 v. above ground will cause a 50 mv. shift in the output plate potential. The equalizing potentiometers 310 of the comparators have been kept to a minimum 68 ohms in order to maintain as large a cfotnpari ator gain .as possible. This implies careful selection of pentodes. It was found that three out of pentode tubes could be compensated by the 68 ohm equalizing potentiometer. It lis therefore assumed that the percentage of usable pentodes for comparator purposes would increase if tubes were used where quality control is much more 20 stringent. Y

The modified analyzer has been packaged and complete` ly checked out. Its performance showed it to be a suf perior unit because of the few simple redesign features'.

The total volume of the complete unit is 5 X 7" x 4%f deep. The size of this unit could be further reduced by the use of subminiature tubes and subminiature potentie ometers.

Where space and Weight permit .the modification of FIG. 1l would be used and the construction of FIG. l 30 used only under extremes of space or weight limitation.

For purpose of illustration particular embodiments of the invention have been illustrated and described according to the best present understanding thereof. However,

it -will be apparent to those skilled in the art that various 3 changes and modifications in the construction and ar rangement of the parts thereof can be made Without departing from the true spirit and scope of the invention.

I claim:

1. A modulation detector comprising a first and a-second voltage generator, a first and a second difference amplifier, said difference amplifiers being cross connected to said voltage generators, a first and a second level slicer, said Slicers being controlled by the respective difference amplifiers, a first and a second gate tube responsive respectively to said first and second slicers, said gate tubes being connected in parallel to an output circuit and an amplifier between each of said difference amplifiers and its respective Slicer.

2. A modulation detector comprising a first and a second voltage generator, a first and a second difference ampliiier, said difference amplifiers being cross connected to said voltage generators, a first and a second slicer, said Slicers being controlled by the respective difference amplifiers, a first and a second gate tube responsive respectively to said first and second Slicers, said gate tubes being connected in parallel to an output circuit.

5 tude samples at suitable time intervals from said first sequence, means for periodically applying said first and second samples to the respective potential generators, an adder connected to provide the sum of the outputs of said generators, a difference amplifier providing the dif- 10 ference between the outputs of said generators, a comparator responsive to the sum and difference of said outputs of said generators for providing sequential control signals, a gate connected to respond to said control potentials, said gate having a threshold potential applied thereto, and a blocking oscillator controlled by said gate.

4. A modulation detecting system responsive to a first and second series of interspaced amplitude samples of the envelope of a received transmission comprising a first and second potential generator, said first generator providing a series of output potentials controlled by the amplitudes of the first series of samples, said second generator providing a series of output potentials controlled by the amplitudes of the second series of samples, an

adder connected -to provide the sum of outputs of said generators, means providing the difference between said output potentials, a comparator responsive to said sum and difference for providing control potentials, a gate, circuit means for applying said control potentials to said gate, a control circuit for applying read out pulses t0 said gate and a pulse generator controlled by the output of said gate.

5. A statistical analyzer for determining the presence or absence of modulation on a detected radiation comprising a first potential generator providing a first sequence of input potentials proportional to the height of a first sequence of samples of preselected sequential portions of the envelope of a received radiation, a second potential generator providing a second sequence of input potentials proportional to the height of a second sequence of samples of second preselected sequential portions of the envelope taken at a predetermined time relation along the envelope from said firstsamples, a difference amplifier responsive to the output potentials of said generators, an

5 adder connected for obtaining the sum of said output potentials, a comparator providing sequential control potentials dependent on the sequential magnitudes of the sum and difference of said input potentials, a gate having a threshold potential applied thereto, said control potential determining the operations of said gate and a blocking oscillator responsive to the operation of said gate.

Gerks Jan. 29, 1957 Raisbeck Sept. 30, 1958 

2. A MODULATION DETECTOR COMPRISING A FIRST AND A SECOND VOLTAGE GENERATOR, A FIRST AND A SECOND DIFFERENCE AMPLIFIER, SAID DIFFERENCE AMPLIFIERS BEING CROSS CONNECTED TO SAID VOLTAGE GENERATORS, A FIRST AND A SECOND SLICER, SAID SLICERS BEING CONTROLLED BY THE RESPECTIVE DIFFERENCE AMPLIFIERS, A FIRST AND A SECOND GATE TUBE RESPONSIVE RESPECTIVELY TO SAID FIRST AND SECOND SLICERS, SAID GATE TUBES BEING CONNECTED IN PARALLEL TO AN OUTPUT CIRCUIT. 